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ics for communications pll-frequency synthesizer pmb2306r/pmb2306t version 2.2 data sheet 02.97 t2306-0v22-d1-7600
(glwlrq this edition was realized using the software system framemaker a . 3xeolvkhge\ 6lhphqv$* +/,7 ? 6lhphqv$* $oo5ljkwv5hvhuyhg $wwhqwlrqsohdvh as far as patents or other rights of third parties are concerned, liability is only assumed for components, not for applications, processes and circuits implemented within components or assemblies. the information describes the type of component and shall not be considered as assured characteristics. terms of delivery and rights to change design reserved. for questions on technology, delivery and prices please contact the semiconductor group offices in germany or the siemens companies and representatives worldwide (see address list). due to technical requirements components may contain dangerous substances. for information on the types in question please contact your nearest siemens office, semiconductor group. siemens ag is an approved cecc manufacturer. 3dfnlqj please use the recycling operators known to you. we can also help you C get in touch with your nearest sales office. by agreement we will take packing material back, if it is sorted. you must bear the costs of transport. for packing material that is returned to us unsorted or which we are not obliged to accept, we shall have to invoice you for any costs incurred. &rpsrqhqwvxvhglqolihvxssruwghylfhvruv\vwhpvpxvwehh[suhvvo\dxwkrul]hgiruvxfksxusrvh critical components 1 of the semiconductor group of siemens ag, may only be used in life-support devices or systems 2 with the express written approval of the semiconductor group of siemens ag. 30%530%7 5hylvlrq+lvwru\ &xuuhqw9huvlrq previous version: 01.94 page (in previous version) page (in new version) subjects (major changes since last revision) 14-15 19-20 $&'&&kdudfwhulvwlfv h-input current , h : is changed from 10 m a to 30 m a and l-input current , l : is changed from -10 m a to -30 m a 26 26 &orfniuhtxhqf\ i cl max. is changed from 10mhz to 12mhz; +sxovhzlgwk&/ w whcl min. is changed from 60ns to 40ns; +sxovhzlgwkhqdeoh w when min. is changed from 60ns to 40ns; 18 18 input reference frequency i cri is changed from 20mhz to 22mhz 19 19 ,qsxw6ljqdo5, input voltage 9 i : is changed from 20mhz to 22mhz
30%530%7 7deohri&rqwhqwv 3djh semiconductor group 3 02.97 2yhuylhz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 1.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 1.2 pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5 1.3 pin definitions and functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6 1.4 functional block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 &lufxlw'hvfulswlrq . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 (ohfwulfdo&kdudfwhulvwlfv . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 3.1 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 3.2 typical supply current , dd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 3.3 ac/dc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 3dfndjh2xwolqhv . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34 4.1 plastic-package, p-tssop-16 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34 4.2 plastic-package, p-dso-14-1(smd) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35
30%5 376623 3'62 30%7 semiconductor group 4 02.97 3//)uhtxhqf\6\qwkhvl]hu 30%530%7 9huvlrq %lsrodu,& the pmb 2306t pll is a high speed cmos ic, especially designed for use in battery powered radio equipment and mobile telephones. the primary applications will be in digital systems e.g. gsm, pcn, adc, jdc and dect systems. the wide range of dividing ratios also allows application in modern analog systems 7\sh 9huvlrq 2ughulqj&rgh 3dfndjh pmb 2306t v2.2 Q67100-H6423 p-dso-14 (smd) pmb 2306t v2.2 q67106-h6423 p-dso-14 (smd, tape & reel) pmb 2306r v2.2 q-67106-h6514 (t&r) p-tssop-16 (smd, t&r) ? serial control (3-wire bus: data, clock, enable) for fast programming ( i max ~ 10 mhz) ? switchable polarity and phase detector current programmable ? 2 multifunction outputs ? digital phase detector output signals (e.g. for external charge pump) ? i rn , i vn outputs of the r and n scalers ? port 1 output (e.g. for standby of the prescaler) ? external current setting for pd output ? lock detect output with gated anti-backlash pulse (quasi digital lock detect) 2yhuylhz )hdwxuhv ? low operating current consumption (typically 3.5 ma) ? high input sensitivity, high input frequencies (220 mhz) ? extremely fast phase detector without dead zone ? linearization of the phase detector output by current sources ? synchronous programming of the counters (n-, n/a-, r-counters) and system parameters ? fast modulus switchover for 65-mhz operation ? switchable modulus trigger edge ? large dividing ratios for small channel spacing a scaler 0 to 127 n scaler 3 to 16.380 r scaler 3 to 65.535
30%530%7 2yhuylhz semiconductor group 5 02.97 3lq&rqiljxudwlrq (top view) 3'62 376623 mfo1 v ss en da nc clk ri v dd nc v ss1 ld fi mfo2 v dd1 mod pd
30%530%7 2yhuylhz semiconductor group 6 02.97 3lq'hilqlwlrqvdqg)xqfwlrqv 7deoh '62 76623 6\pero )xqfwlrq 66 9 dd positive supply voltage for serial control logic. 22 9 ss ground for serial control logic. 11 13 9 dd 1 positive supply voltage for the preamplifiers, counters, phase detector and charge pump. 911 9 ss 1 ground for the preamplifiers, counters, phase detector and charge pump. ( 1rwh7khslqv 9 '' dqg 9 '' uhvshfwlyho\ 9 66 dqg 9 66 kdyhwrkdyhwkhvdphvxsso\yrowdjh .) 33 en /lqh%xv(qdeoh enable line of the serial control with internal pull-up resistor. when en = h the input signals clk and da are disabled internally. when en = l the serial control is activated. the received data are transferred into the latches with the positive edge of the en-signal. 44 da /lqh%xv'dwd serial data input with internal pull-up resistor. the last two bits before the en-signal define the destination address. in a byte- oriented data structure the transmitted data have to end with the en-signal, i.e. bits to be filled in (dont care) are transmitted first. 55 clk /lqh%xv&orfn clock line with internal pull-up resistor. the serial data are read into the internal shift register with the positive edge (see pulse diagram for serial data control). 77 mod 0rgxoxv&rqwuro2xwsxw for external dual modulus prescaler. the modulus output is low at the beginning of the cycle. when the a-counter has reached its set value, mod switches to high. when the n-counter has reached its set value, mod switches to low again, and the cycle starts from the top. when the prescaler has the counter factor p or p + 1 (p for mod = h, p + 1 for mod = l), the overall scaling factor is np + a. the value of the a- counter must be smaller than that of the n-counter. the trigger edge of the modulus signal to the input signal can be selected (see programming tables and mod a, b) according to the needs of the prescaler. in single modulus operation and for standby operation in dual modulus operation, the output is low.
30%530%7 2yhuylhz semiconductor group 7 02.97 810 fi 9&2)uhtxhqf\ input with highly sensitive preamplifier for 14-bit n-counter and 7-bit a-counter. with small input signals ac coupling must be set up, where dc coupling can be used for large input signals. 11 ri 5hihuhqfh)uhtxhqf\ input with highly sensitive preamplifier for 16-bit r-counter. with small input signals ac coupling must be set up, where dc coupling can be used for large input signals. 10 12 pd 3kdvh'hwhfwru tristate charge pump output. the integrated, positive and negative current sources can be programmed with respect to their current density by means of the serial control. activation and deactivation depend on the phase relationship of the scaled-down input signals fi:n, ri:r. (see phase detector output waveforms.) frequency i v < i r or i v lagging: p-channel current source active frequency i v > i r or i r leading: n-channel current source active frequency i v = i r and pll locked: current sources are switched off, pd-output is tristate in standby mode the pd-output is set to tristate. the assignment of the current sources to the output signals of the phase detector can be swapped in its polarity, i.e. the sign of the phase detector constant can be controlled. 14 16 ld /rfn'hwhfwru2xwsxw (open drain). unipolar output of the phase detector in the form of a pulse-width modulated signal. the l-pulse width corresponds to the phase difference. phase differences < 20 ns are not indicated due to gating of the antibacklash impuls. in the locked state the ld-signal is at h-level. in standby mode the output is resistive. only for abl status 11 no gating of abl impulse is performed. 7deoh '62 76623 6\pero )xqfwlrq
30%530%7 2yhuylhz semiconductor group 8 02.97 12 14 mfo1 0xowlixqfwlrq2xwsxw for the signals i rn , f v , f vn and port 1. 13 15 mfo2 0xowlixqfwlrq,23lq for the output signals i vn , f rn and the input signal , ref . C the signals f r and f v are the digital output signals of the phase and frequency detector for use in external active current sources (see phase detector output wave forms). C the signals i rn and i vn are the scaled down signals of the reference frequency and vco-frequency. the l-time corresponds to 1/ i ri and 1/ i fi respectively. C in the port function the port 1 output signal is assigned to the information of the status program. the output switches with the rising edge of the en-signal. the standby mode does not affect the port function. C in the internal charge pump mode the input signal , ref determines the value of the pd-output current. reference current for charge pump : , ref = ( 9 dd C 9 ref )/ r1 = 100 m a (tolerance of 20% or less is recommended ) r1: see application circuit 9 ref : see ac/dc characteristics 7deoh '62 76623 6\pero )xqfwlrq
30%530%7 2yhuylhz semiconductor group 9 02.97 )xqfwlrqdo%orfn'ldjudp
30%530%7 &lufxlw'hvfulswlrq semiconductor group 10 02.97 &lufxlw'hvfulswlrq *hqhudo'hvfulswlrq the circuit consists of a reference-, a- and n-counter, a dual modulus control logic, a phase detector with charge pump output and a serial control logic. the setting of the operating mode and the selection of the counter ratios is done serially at the ports clk, da and en. the operating modes allow the selection of single or dual operation, asynchronous or synchronous data acquisition, 4 different antibacklash-impulse times, 8 different pd- output current modes, polarity setting of the pd-output signal, adjustment of the trigger- edge of the mod-output signal, 2 standby modes and the control of the multifunction outputs mfo1 and mfo2. the reference frequency is applied at the ri-input and scaled down by the r-counter. its maximum value is 100 mhz. the vco-frequency is applied at the fi-input and scaled down by the n- or n/a-counter according to single or dual mode operation. the maximum value at fi is 220 mhz at single-, and 65 mhz at dual mode operation. the phase and frequency sensitive phase detector produces an output signal with adjustable anti-backlash impulses in order to prevent a dead zone for very small phase deviations. phase differences of less than 100 ps can be resolved. in general the shortest anti-backlash pulse gives the best system performance. 3urjudpplqj programming of the ic is done by a serial data control. the contents of the message are assigned to the functional units according to the address. 6lqjoh ru gxdo prgh rshudwlrq dv zhoo dv dv\qfkurqrxv ru v\qfkurqrxv gdwd dftxlvlwlrq lv vhw e\ vwdwxvdqgvkrxogwkhuhiruhsuhfhghwkhsurjudpplqjriwkhfrxqwhuv 'dwddftxlvlwlrq the pmb 2306t offers the possibility of synchronous data acquisition to avoid error signals at the phase detector due to non-corresponding dividing factors in the counters produced by asynchronous loading. synchronous programming guarantees control during changes of frequency or channel. that means that the state of the phase detector or the phase difference is kept maintained, and in case of lock in, the control process starts with the phase difference zero.
30%530%7 &lufxlw'hvfulswlrq semiconductor group 11 02.97 this is done as follows: 1.setting of synchronous data acquisition by status 2. 2.programming of the r-counter, status 1 (optional)-data is being loaded into shadow registers. 3.programming of the n- or n/a-counter-data is being loaded into shadow registers, the en-signal starts the synchronous loading procedure. 4. synchronous programming C which means data transfer of all data from the shadow registers to the data registers C takes place at that point in time when the respective counter reaches zero + 1, the maximum repetition rate for channel change is therefore i fi :n. 5.transfer of status 1 information into the corresponding data register is tied to the n- counter loading, but follows the loading of the n-data register in the distance of one n- counter dividing ratio, this guarantees that for example a new pd-current value becomes valid at the same time when the counters are loaded with the new data. synchronous avoids additional phase error caused by programming. synchronous data acquisition is of especial advantage, when large steps in frequency are to be made in a short time. for this purpose a high reference frequency can be programmed in order to achieve rapid C rough C transient response. this method increases the fundamental frequency nearly by the square route of the reference frequency relation. when rough lock is achieved, another synchronous data transfer is needed to switch back to the original channel spacing. a fine lock in will finish the total step response. it may not be necessary to change reference frequency, but it make sense to perform synchronous data acquisition in any case. especially for gsm, pcn, dect, damps, jdc, php systems the synchronous mode should be used to get best performance of the pmb 2306t. 6wdqge\&rqglwlrq the pmb 2306t has two standby modes (standby 1, 2) to reduce the current consumption. standby 1 switches off the whole circuit, the current consumption is reduced below 1 m a. standby 2 switches off the counters, the charge pump and the outputs, only the preamplifiers stay active. the standby modes do not affect the port output signal. for the influence on the other output signals vhhvwdqge\wdeoh 1rwh i 51 i 91 f 51 dqg f 91 duhwkhlqyhuwhgvljqdovri i 5 i 9 f 5 dqg f 9
30%530%7 &lufxlw'hvfulswlrq semiconductor group 12 02.97 3urjudpplqj7deohv 3urjudpplqj7deohv (contd) * in general the shortest anti-backlash pulse gives the best system performance. ** no abl (anti-backlash-pulse) gating performed. this means, that at the ld output the anti-backlash pulse will appear. in the other cases the anti-backlash pulse will be surpressed at the ld output. 6wdwxv%lwv 0xowlixqfwlrq2xwsxwv 0rgh 0rgh 0)2 0)2 5hpdunv 00 i rn i vn test mode 01 f v f rn external charge pump mode 1 10 f vn f rn external charge pump mode 2 11port 1 , ref internal charge pump mode 6wdwxv%lwv 3'&xuuhqw0rgh 3'&xuuhqw 3'&xuuhqw 3'&xuuhqw 0 000.175 0 010.25 0 100.35 0 110.5 1 000.7 1 011 1 101.4 1 112 6wdwxv%lwv $qwl%dfnodvk 3xovh:lgwk $qwl%dfnodvk 3xovh:lgwk w z w\s >qv@ $ssolfdwlrq 001.3* 9 dd = 5 v 015 1 0 10 not recommended 1 1 13** any application where continuous lock detect required
30%530%7 &lufxlw'hvfulswlrq semiconductor group 13 02.97 6wdqge\7deoh 6wdwxv%lwv 3uhdpsolilhu)xqfwlrq0rgh 6lqjoh'xdo 0rgh 3uhdpsolilhu 6hohfw 0 0 fi-input frequency, single hf-mode 0 1 fi-input frequency, single lf-mode 1 0 fi-input frequency, dual mode, fi-trigger edge lh, mod a 1 1 fi-input frequency, dual mode, fi-trigger edge hl, mod b 2xwsxw3lqv 6wdwxv 0)2 0)2 /' 3' 02' f 9 f 91 standby 1 low high high resistive tristate low standby 2 low high high resistive tristate low
30%530%7 &lufxlw'hvfulswlrq semiconductor group 14 02.97 6huldo&rqwuro'dwd)rupdwvwdwxv 6wdwxv 6wdwxv 6lqjohrugxdoprghrshudwlrqdvzhoodvdv\qfkurqrxvruv\qfkurqrxvgdwd dftxlvlwlrqlvvhwe\vwdwxvdqgvkrxogwkhuhiruhsuhfhghwkhsurjudpplqjri wkhfrxqwhuvvhhdovrsdjh 1 2 3 4 5 6 en 13 14 15 16 7 8 9 10 11 12 1 2 3 4 5 6 en pd-current 2 pd-current 3 0 address 0 01 anti-backlash pulse width 1 anti-backlash pulse width 2 preamplifier select single / dual mode port 1 pd-current 1 data acquisition mode mode 1 mode 2 pd-polarity standby 1 standby 2 see table see table see table see table see table single dual low high see table asynchronous synchronous see table see table negative positive standby active standby active 01
30%530%7 &lufxlw'hvfulswlrq semiconductor group 15 02.97 6huldo&rqwuro'dwd)rupdwqqdfrxqwhu 'xdo0rgh 6lqjoh0rgh 20 21 22 23 14 15 16 17 18 19 8 9 10 11 12 13 en 11 0 address 0 lsb 2 3 4 5 6 7 1 13 14 15 16 7 8 9 10 11 12 1 2 3 4 5 6 en msb lsb msb n-counter a-counter lsb msb
30%530%7 &lufxlw'hvfulswlrq semiconductor group 16 02.97 6huldo&rqwuro'dwd)rupdwufrxqwhu 14 15 16 17 18 en 8 9 10 11 12 13 1 1 lsb 2 3 4 5 6 7 1 msb r-counter address
30%530%7 &lufxlw'hvfulswlrq semiconductor group 17 02.97 3kdvh'hwhfwruq2xwsxw:dyhirupv
30%530%7 (ohfwulfdo&kdudfwhulvwlfv semiconductor group 18 02.97 (ohfwulfdo&kdudfwhulvwlfv $evroxwh0d[lpxp5dwlqjv 7 a = C 40 to 85 c all pins are protected against esd. unused inputs without pullup resistors must be connected to either 9 dd or 9 ss . 7\slfdo6xsso\&xuuhqw , '' 3dudphwhu 6\pero /lplw9doxhv 8qlw 5hpdunv plq pd[ supply voltage 9 dd C0.3 6 v input voltage 9 i C0.3 9 dd + 0.3 v output voltage 9 q gnd 9 dd v power dissipation per output 3 q 10 mw total power dissipation 3 tot 300 mw ambient temperature 7 a C 40 85 c in operation storage temperature 7 stg C 50 125 c 2shudwlqj5dqjh supply voltage 9 dd 3.0 5.5 v input frequency dual mode input frequency single hf-mode input frequency single lf-mode input reference frequency input frequency dual mode input frequency single hf-mode input frequency single lf-mode input reference frequency i fi i fi i fi i ri i fi i fi i fi i ri 0.1 0.1 0.1 0.1 0.1 0.1 65 220 90 100 30 120 35 22 mhz mhz mhz mhz mhz mhz mhz mhz 9 dd = 4.55.5v 9 dd = 4.55.5v 9 dd = 4.55.5v 9 dd = 4.55.5v 9 dd = 3.3 v 9 dd = 3.3 v 9 dd = 3.3 v 9 dd = 3.3 v pd-output current pd-output voltage pd-output voltage / , pd / 9 pd 9 pd 0.5 0.5 4 9 dd C0.5 9 dd C0.5 ma v v 9 dd = 4.5C5.5v 9 dd = 3.3 v ambient temperature 7 a C40 85 c supply voltage 9 dd 3.3 5 5.5 v test conditions: supply current singlemode hf dual mode standby 2 standby 1 , dd , dd , dd , dd 1.63 1.76 0.11 2.6 2.80 0.62 2.94 3.17 0.75 1 ma ma ma m a i fi = 50 mhz, 9 fi = 150 mvrms i ri = 10 mhz, 9 ri = 150 mvrms , pd = 0.25 ma, , ref = 100 m a
30%530%7 (ohfwulfdo&kdudfwhulvwlfv semiconductor group 19 02.97 $&'&&kdudfwhulvwlfv 3dudphwhu 6\pero /lplw9doxhv 8qlw 7hvw&rqglwlrq plq w\s pd[ ,qsxw6ljqdov'$&/.(1zlwklqwhuqdosxooxsuhvlvwruv h-input voltage l-input voltage input capacity h-input current l-input current 9 ih 9 il & i , h , l 0.7 9 d d 0 C300 9 dd 0.3 9 dd 5 10 v v pf m a m a 9 i = 9 dd = 5.5 v 9 i = gnd further information about timing see at page 25 and 26 ,qsxw6ljqdo5, input voltage input voltage slew rate input capacity h-input current l-input current 9 i 9 i & i , h , l 100 100 2.5 C30 3 30 mvrms mvrms v/ m s pf m a m a i = 4 100 mhz, 9 dd =4.5 v i = 4 22 mhz, 9 dd = 3.3 v 9 dd = 3.3 5.5 v 9 i = 9 dd = 5.5 v 9 i = gnd ,qsxw6ljqdo),gxdoprgh input voltage input voltage input voltage slew rate input capacity h-input current l-input current 9 i 9 i 9 i & i , h , l 180 180 50 4 C30 3 30 mvrms mvrms mvrms v/ m s pf m a m a i = 4 65 mhz, 9 dd = 4.5 v i = 4 30 mhz, 9 dd = 3.3 v i = 10 30 mhz, 9 dd = 3.3 v 9 dd = 3.3 5.5 v 9 i = 9 dd = 5.5 v 9 i = gnd ,qsxw6ljqdo),vlqjoh+)prgh input voltage input voltage input voltage slew rate input capacity h-input current l-input current 9 i 9 i 9 i & i , h , l 200 20 50 2.5 C30 3 30 mvrms mvrms mvrms v/ m s pf m a m a i = 4 220 mhz, 9 dd = 4.5 v i = 4120mhz, 9 dd = 3.3 v i = 10 50 mhz, 9 dd = 4.5 v 9 dd = 3.3 5.5 v 9 i = 9 dd = 5.5 v 9 i = gnd
30%530%7 (ohfwulfdo&kdudfwhulvwlfv semiconductor group 20 02.97 ,qsxw6ljqdo),vlqjoh/)prgh input voltage input voltage slew rate input capacity h-input current l-input current 9 i 9 i & i , h , l 100 100 2.5 C30 3 30 mvrms mvrms v/ m s pf m a m a i = 4 90 mhz, 9 dd = 4.5 v i = 4 35 mhz, 9 dd = 3.3 v 9 dd = 3.3 5.5 v 9 i = 9 dd = 5.5 v 9 i = gnd 2xwsxw&xuuhqw , 3' current mode 0.175 ma 0.25 ma 0.35 ma 0.5 ma 0.7 ma 1.0 ma 1.4 ma 2.0 ma standby * guaranteed by design , prog , prog , prog , prog , prog , prog , prog , prog / , pd / C 20 % C 20 % C 20 % C 20 % C 20 % C 10 % C 10 % C 10 % 0.1* + 20 % + 20 % + 20 % + 20 % + 20 % + 10 % + 10 % + 10 % 50 ma ma ma ma ma ma ma ma na 9 dd = 4.5 5.5 v 9 pd = 9 dd /2 , ref = 100 m a 9 dd = 5.5 v 2xwsxw7rohudqfhv , 3' d , pd / , prog d , pd / , prog C20% 4% +3% 9 pd = 9 dd /2, 9 dd = 3.3 v 9 pd = 14v, 9 dd = 5 v ,qsxw9rowdjh0)2lqwhuqdofkdujhsxpsprgh reference voltage 9 ref 0.9 1.1 1.3 v 9 dd = 4.5 5.5 v, , ref = 100 m a 3dudphwhu 6\pero /lplw9doxhv 8qlw 7hvw&rqglwlrq plq w\s pd[
30%530%7 (ohfwulfdo&kdudfwhulvwlfv semiconductor group 21 02.97 2xwsxw6ljqdo0)2sxvksxoo h-output voltage l-output voltage h-output voltage l-output voltage rise time fall time rise time fall time 9 qh 9 ql 9 qh 9 ql w r w f w r w f 9 dd C1 9 dd C1 2.5 2.0 4.0 2.5 1 1 10 10 10 10 v v v v ns ns ns ns 9 dd = 4.5 5.5 v, , qh = 2 ma 9 dd = 4.5 5.5 v, , ql = 2 ma 9 dd = 3.3 v, , qh = 1.2 ma 9 dd = 3.3 v, , ql = 1.2 ma 9 dd = 4.5 5.5 v, & i = 10 pf 9 dd = 4.5 5.5 v, & i = 10 pf 9 dd = 3.3 v, & i = 10 pf 9 dd = 3.3 v, & i = 10 pf 2xwsxw6ljqdo0)2sxvksxoo h-output voltage l-output voltage h-output voltage l-output voltage rise time fall time rise time fall time 9 qh 9 ql 9 qh 9 ql w r w f w r w f 9 dd C1 9 dd C1 2 2 3 3 1 1 10 10 10 10 v v v v ns ns ns ns 9 dd = 4.5 5.5 v, , qh = 2 ma 9 dd = 4.5 5.5 v, , ql = 2 ma 9 dd = 3.3 v, , qh = 1.2 ma 9 dd = 3.3 v, , ql = 1.2 ma 9 dd = 4.5 5.5 v, & i = 10 pf 9 dd = 4.5 5.5 v, & i = 10 pf 9 dd = 3.3 v, & i = 10 pf 9 dd = 3.3 v, & i = 10 pf 2xwsxw6ljqdo/'qfkdqqhorshqgudlq l-output voltage l-output voltage fall time fall time 9 ql 9 ql w f w f 3 4.5 0.4 0.4 10 10 v v ns ns 9 dd = 4.5 5.5 v, , ql = 0.5 ma 9 dd = 3.3 v, , ql = 0.5 ma 9 dd = 4.5 5.5 v, & i = 10 pf 9 dd = 3.3 v, & i = 10 pf 3dudphwhu 6\pero /lplw9doxhv 8qlw 7hvw&rqglwlrq plq w\s pd[
30%530%7 (ohfwulfdo&kdudfwhulvwlfv semiconductor group 22 02.97 2xwsxw6ljqdo02'sxvksxoo h-output voltage l-output voltage h-output voltage l-output voltage rise time fall time propagation delay time h-l to fi propagation delay time l-h to fi rise time fall time propagation delay time h-l to fi propagation delay time l-h to fi 9 qh 9 ql 9 qh 9 ql w r w f w dqhl w dqlh w r w f w dqhl w dqlh 9 dd C0.4 9 dd C0.4 1.5 1.3 8 8 2.8 1.6 12 12 0.4 0.4 3 3 12 12 4 4 v v v v ns ns ns ns ns ns ns ns 9 dd = 4.5 5.5 v, , qh = 0.5 ma 9 dd = 4.5 5.5 v, , ql = 0.5 ma 9 dd = 3.3 v, , qh = 0.3 ma 9 dd = 3.3 v, , ql = 0.3 ma 9 dd = 4.5 5.5 v, & i = 5 pf 9 dd = 4.5 5.5 v, & i = 5 pf 9 dd = 4.5 5.5 v, & i = 5 pf 9 dd = 4.5 5.5 v, & i = 5 pf 9 dd = 3.3 v, & i = 5 pf 9 dd = 3.3 v, & i = 5 pf 9 dd = 3.3 v, & i = 5 pf 9 dd = 3.3 v, & i = 5 pf 3dudphwhu 6\pero /lplw9doxhv 8qlw 7hvw&rqglwlrq plq w\s pd[
30%530%7 (ohfwulfdo&kdudfwhulvwlfv semiconductor group 23 02.97 (txlydohqw,26fkhpdwlfv
30%530%7 (ohfwulfdo&kdudfwhulvwlfv semiconductor group 24 02.97 (txlydohqw,26fkhpdwlfv (contd) 500k w
30%530%7 (ohfwulfdo&kdudfwhulvwlfv semiconductor group 25 02.97 3xovh'ldjudp
30%530%7 (ohfwulfdo&kdudfwhulvwlfv semiconductor group 26 02.97 6huldo&rqwuro'dwd,qsxw7lplqj 3dudphwhu 6\pero /lplw9doxhv 8qlw 7hvw&rqglwlrq plq pd[ clock frequency i cl 12 mhz 9 dd =3.3v h-pulsewidth (cl) w whcl 40 ns data setup w ds 20 ns setup time clock-enable w cle 20 ns setup time enable-clock w ecl 20 ns h-pulsewidth (enable) w when 40 ns rise, fall time w r w f 10 m s propagation delay time en-port w dep 1 m s
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30%530%7 (ohfwulfdo&kdudfwhulvwlfv semiconductor group 28 02.97 *60$ssolfdwlrq&lufxlw t 4
30%530%7 (ohfwulfdo&kdudfwhulvwlfv semiconductor group 29 02.97 /lvwri&rpsrqhqwv ,whp 4xdqwlw\5hihuhqfh 3duw 11 5 7 100 w smd/0805 b54102-a1101-k60 s+m 22 5 13 , 5 14 150 w smd/0805 b54102-a1151-j60 s+m 31 5 6 220 w smd/0805 b54102-a1221-j60 s+m 41 5 8 330 w smd/0805 b54102-a1331-j60 s+m 51 5 10 3.3 k w smd/0805 b54102-a1332-j60 s+m 61 5 12 6.8 k w smd/0805 b54102-a1682-j60 s+m 74 5 9 , 5 3 , 5 5 , 5 11 8.2 k w smd/0805 b54102-a1822-j60 s+m 81 5 4 18 k w smd/0805 b54102-a1183-j60 s+m 91 5 2 22 k w smd/0805 b54102-a1223-j60 s+m 10 1 5 2 39 k w smd/0805 b54102-a1393-j60 s+m 11 1 / 1 22 nh simid 01 b82412-a3220-m s+m 12 1 & 11 1.2 pf cog/0805 b37940-k5010-c262 s+m 13 1 & 13 2.2 pf cog/0805 b37940-k5020-c262 s+m 14 1 & 8 10 pf cog/0805 b37940-k5100-j62 s+m 15 6 & 20 , & 10 , & 12 , & 14 , & 15 , & 16 22 pf cog/0805 b37940-k5220-j62 s+m 16 3 & 17 , & 1 , & 2 33 pf cog/0805 b37940-k5330-j62 s+m 17 1 & 9 100 pf cog/0805 b37940-k5101-j62 s+m 18 1 & 3 330 pf cog/0805 b37940-k5331-j62 s+m 19 1 & 5 560 pf cog/0805 b37940-k5561-j62 s+m 20 1 & 7 5.6 nf cog/1210 b37949-k5562-j62 s+m 21 1 & 6 100 nf x7r/1210 b37950-k5104-k62 s+m 22 1 & 19 22 m f b45196-e3226-+409 s+m 23 1 d1 bby 51 q62702-b631 siemens 24 2 t3, t2 bfr 280 q62702-f1298 siemens 25 1 t1 bft 92 q62702-f1062 siemens 26 1 & 4 1,0 nf cog/1210 b37949-k5102-j62 s+m 27 2 x2, x1 sma connector 28 1 rx 1.3 ghz b69610-g1307-a412 s+m 29 1 ic1 pmb 2306t p-dso-14 Q67100-H6423 siemens pmb 2306t p-dso-14 q67106-h6423(t+r) siemens 30 1 ic2 pmb 2314 p-dso-8 q67000-a6121 siemens pmb 2314 p-dso-8 q67006-a6121(t+r) siemens
30%530%7 (ohfwulfdo&kdudfwhulvwlfv semiconductor group 30 02.97 3kdvh1rlvh&orvhwrwkh&duulhu
30%530%7 (ohfwulfdo&kdudfwhulvwlfv semiconductor group 31 02.97 6shfwuxpdw/rzhu(qgri*607;%rdug0reloh
30%530%7 (ohfwulfdo&kdudfwhulvwlfv semiconductor group 32 02.97 /rfn,q7lphiru*60$ssolfdwlrq
30%530%7 (ohfwulfdo&kdudfwhulvwlfv semiconductor group 33 02.97 0hdvxuhphqw6hw8siru/rfn,q7lph
30%530%7 3dfndjh2xwolqhv semiconductor group 34 02.97 3dfndjh2xwolqhv 3odvwlf3dfndjh376623
30%530%7 3dfndjh2xwolqhv semiconductor group 35 02.97 3odvwlf3dfndjh3'6260' gpm05247 6ruwvri3dfnlqj package outlines for tubes, trays etc. are contained in our data book package information. dimensions in mm smd = surface mounted device

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